Capacitive micromachined ultrasonic transducers (CMUT) have gained much attention as an ultrasound transducer technology to complement/replace piezoelectric transducers. CMUTs have been shown to enhance existing medical ultrasound imaging probes, and new applications inappropriate for piezoelectrics have been explored using CMUTs. In medical imaging, examples include annular ring-shaped arrays, micro-linear arrays, fully populated 2D arrays, flexible arrays, and 2D reconfigurable arrays. In medical therapy, CMUTs can provide MR-compatible high-intensity focused ultrasound (HIFU). New designs and fabrication methods have been proposed to improve the performance and reliability of CMUTs such as direct wafer-to-wafer fusion bonding. Waferbonding offers unparalleled fabrication flexibility as well as improved device performance and uniformity, when compared to the traditional surface micromachining technique. Coupled with innovative designs, wafer-bonded CMUTs have delivered high output pressures, while retaining the expected wide fractional bandwidth. To further realize the potential of the wafer-bonded CMUTs for medical imaging applications, it is highly desired to incorporate through-wafer electrical interconnects with wafer-bonded devices so that the CMUT arrays can be directly integrated with a front-end IC by flip-chip bonding.
Through-wafer interconnects are a compact means of providing electrical connections to CMUT elements. These interconnects are necessary in situations where direct wire bonding to array elements is not feasible such as in fully populated 2D arrays; or due to space constraints, e.g., CMUTs for catheter-based applications. Researchers have reported on interconnect techniques both based on through-wafer vias and through-wafer trench isolation. In the through-wafer via implementation, a conductive material, usually doped polysilicon, is used to fill the vias through the several hundred micron thick silicon substrate. This material serves as the conductor between the front side of a silicon wafer, where the CMUT elements reside, and the backside of the wafer, where the flip-chip bond pads are located.
Integrating through-wafer vias with CMUTs is a complex process requiring many lithographic steps. After the deposition of the polysilicon, performing wafer-to-wafer fusion bonding is difficult. The complex through-wafer interconnect fabrication steps degrade wafer surface smoothness; therefore, an expensive chemical-mechanical polishing step is required to get bondable surface quality in terms of roughness. Furthermore, these steps add stress to the wafer, which results in a reduced radius of curvature. To date, no successful through-wafer via fabrication technique has been demonstrated that is compatible with the wafer-bonding technique of making CMUTs. On the other hand, the fabrication process for CMUTs with frameless trench isolation is significantly simpler than through-wafer via process. In that implementation, a carrier wafer is required during the deep reactive ion etching (DRIE) and the flip-chip bonding steps to provide mechanical support for the membranes. This particular requirement presents drawbacks in the fabrication process. Good adhesion between the carrier wafer and the membrane surface is required for adequate mechanical support for the membranes. However, it is then a challenge to separate the carrier wafer and the membrane after the flip-chip bonding. The adhesive material can swell in the solvent and, therefore, create stress that can break the CMUT membranes.
Current fabrication methods include using a carrier wafer during the fabrication process, which generally includes a large number of fabrication steps. Further, the CMUT cell is unprotected during the fabrication process, resulting in contamination of the cell cavity. The resultant CMUT cells have limited design flexibility and suffer from reliability degradation due to electrical breakdown.
Accordingly, there is a need to develop a CMUT structure and fabrication method that reduces the number of fabrications steps, improves CMUT cell structure by increasing electrical breakdown voltage and reducing parasitic capacitance, provides better design flexibility and high controllability for the whole frequency range in which CMUT cells can be used (1 kHz-300 MHz), and further provides a built-in support structure that eliminates the need of a carrier wafer during the fabrication process. What is further needed is a CMUT cell that is completely protected mechanically and protected against contaminations by the membrane silicon-on-insulator (SOI) wafer in an early stage of the fabrication.